As is well known in the art, a semiconductor device testing apparatus (commonly called device tester or IC tester) uses a pattern generator which generates a test signal having a predetermined pattern, an address signal and a control signal all of which are to be applied to a semiconductor device under test (hereinafter referred to as DUT), an expected value signal having a predetermined pattern to be supplied to logical comparator means, and the like.
FIG. 9 is a block diagram schematically depicting the circuit configuration of an example of the conventional pattern generator of this type. This pattern generator comprises a vector generation control (VGC) 1, a control table buffer (CTB) 2, a group of test pattern storages or truth table buffers (TTB) 3, a scan pattern generator (SCPG) 4, a programmable data selector (PDS) 5, a group of OR circuits 6, and a group of frame processors (FP) 7. The truth table buffers 3, the OR circuits 6 and the frame processors 7 are prepared equal in their number to the number of pins of a DUT 8.
The vector generation control 1 has instructions previously stored therein for controlling a pattern generation sequence in a pattern program, and normally generates an address of pattern data stored in one of the truth table buffers 3. In addition, it controls the scan pattern generator 4, etc. Further, the truth table buffers 3 have pattern data previously stored therein which are necessary for causing the pattern generator to generate various test patterns therefrom.
In the control table buffer 2 there are previously stored a match (coincidence) mode designation instruction and a timing switching instruction that are control signals in the pattern program. The match mode mentioned herein refers to a mode in which, when an output signal from the DUT 8 coincides with an expected value signal, the test pattern generation sequence of a functional test is altered in real time.
The scan pattern generator 4 is an optional hardware for storing and generating a scan pattern which is necessary for implementing LSSD (level sensitive scan design that is a scan design scheme developed by IBM Inc. of United States). The scan pattern refers to a pattern that is applied to a test pin or pins added to a device which can undergo a scan path test. The scan path test refers to a test simplified procedure or scheme which permits simplification of the test by connecting in series all of flip-flops of logical circuits in a DUT to operate them as a shift register which means equivalently a combination circuit of all of the flip-flops.
The programmable data selector 5 is a hardware for assigning a scan pattern or a test pattern generated from the scan pattern generator 4 to a desired pin or pins of the DUT 8.
The frame processors 7 are pin signal waveform generating parts each of which generates a waveform of the test pattern to be applied to each pin of the DUT 8 for each frame (a basic unit having a width of one test period). Conventionally, the frame processors are constructed by a combination of a format controller, a timing generator, a logical comparator and a calibration unit. As compared with a conventional shared tester (a device tester of the type in which plural resources such as a timing generator, a reference voltage and the like are used in common to respective pins of a DUT), the frame processors are capable of outputting free timing signals and waveforms independently of respective pins of the DUT.
In the conventional pattern generator of the above construction, the same plurality of the truth table buffers 3, the OR circuits 6 and the frame processors 7 are prepared respectively, the number being equal to that of pins of the DUT 8, and one truth table buffer 3, one OR circuit 6 and one frame processor 7 are connected to each pin of the DUT 8. That is, the truth table buffers 3, the OR circuits 6 and the frame processors 7 are fixedly connected to the pins of the DUT 8 in a one-to-one correspondence relationship between them. Accordingly, when some of the pins of the DUT 8 are unused, the truth table buffers 3, the OR circuits 6 and the frame processors 7 corresponding to such unused pins are left connected thereto. As a result, in case the number of unused pins is large, considerably large numbers of truth table buffers 3, OR circuits 6 and frame processors 7 are being wastfully used.
Incidentally, a test pattern of large capacity may sometimes be required even if a DUT uses at present only a small number of pins, leaving the remaining large number of pins unused. The truth table buffers 3 have previously stored therein various test patterns as mentioned above, and hence if the number of truth table buffers 3 that can be used is small, it is difficult to generate a large capacity test pattern.
As a solution to this problem, it is customary in the prior art to add the scan pattern generator 4 and the programmable data selector 5 to the pattern generator as described above, so that the scan pattern generator 4 can generate a large capacity test pattern suitable for testing the DUT 8 and the programmable data selector 5 assigns the test pattern from the scan pattern generator 4 to a desired pin or pins of the DUT 8. It is needless to say that the scan pattern generator 4 is also used in performing the scan path test.
However, the provision of the scan pattern generator 4 has a drawback that the entire tester arrangement becomes expensive because the scan pattern generator 4 is costly. Furthermore, it is necessary not only to prepare and store a program for the generation of test patterns from the scan pattern generator 4 but also to store a control signal--this inevitably leads to the shortcoming of cumbersome and inefficient task involved. Still another defect resides in that the generation of test patterns from the scan pattern generator 4 lacks flexibility in operation.